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ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 1 ? 2000-2003, 2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . powerpc is a trademark of ibm, inc. all other trademarks are t he property of their respective owners. all specifications are su bject to change without notice. features ? one-time programmable (otp) read-only memory designed to store configurat ion bitstreams of xilinx fpga devices ? simple interface to the fpga ? cascadable for storing longe r or multiple bitstreams ? programmable reset polarity (active high or active low) for compatibility with different fpga solutions ? low-power cmos floating-gate process ? 3.3v supply voltage ? guaranteed 20 year life data retention ? available in compact plastic packages: vq44, pc44, pc20, vo8, and so20 ? programming support by leading programmer manufacturers. ? design support using the ise? foundation? and ise webpack? software. ? dual configuration modes for the xc17v16 and xc17v08 devices ? serial slow/fast configuration (up to 20 mb/s) ? parallel (up to 160 mb/s at 20 mhz) description xilinx introduces the high-den sity xc17v00 family of configuration proms which provide an easy-to-use, cost-effective method for storing large xilinx fpga configuration bitstreams. initia l devices in the 3.3v family are available in 16 mb, 8 mb, 4 mb, 2 mb, and 1 mb densities. see figure 1 and figure 2 for simplified block diagrams of the xc17v00 family. the xc17v00 prom can configure a xilinx fpga using the fpga serial configuration mode interface. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the fpga din pin. the fpga generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when the fpga is in slave serial mode, the prom and the fpga must both be clocked by an incoming signal. the xc17v08 and xc17v16 prom can optionally configure a xilinx fpga using the fpga parallel (selectmap) configuration mode interface. when the fpga is in master selectmap mode, the fpga generates the configuration clock that drives the prom. when the fpga is in slave selectmap mode, an external, free-running oscillator generat es the configuration clock that drives the prom and the fpga. after the rising configuration clock (cclk) edge, data is available on the proms data (d0-d7) pins. the data is clocked into the fpga on the following rising edge of the cclk ( figure 3 ). multiple proms can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family. for device programming, either the xilinx ise foundation or ise webpack software compiles the fpga design file into a standard hex format, which is then transferred to most commercial prom programmers. 0 xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 08 product specification r
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 2 r figure 1: simplified block diagram for xc17v04, xc17v02, and xc17v01 (does not show programming circuit) figure 2: simplified block diagram for xc17v16 and xc17v08 (does not show programming circuit) eprom cell matrix address counter ce data oe output clk v cc v pp gnd ds073_01_072600 tc oe reset/ oe/ reset or ceo eprom cell matrix address counter ce d0 data (serial or parallel mode) oe 8 output clk busy v cc v pp gnd ds073_02_031506 tc oe reset/ oe/ reset or d[1:7] (selectmap interface) ceo 7 7
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 3 r pin description data[0:7] the array data value corresponding to the internal address counter location is output on enabled data[0-7] output pin(s) when ce is active, oe is active, and the internal address counter has not incremented beyond its terminal count (tc) value. otherwise, all data pins are in a high impedance state when ce is inactive, oe is inactive, or the internal address counter has incremented beyond its terminal count (tc) value. the xc17v01, xc17v02, and xc17v04 have only the single data output pin for connection to the fpga serial configuration data input pin. the xc17v08 and xc17v16 have the d[0-7] output pins. during device programming, the xc17v08 and xc17v16 must be programmed for use in either serial output mode or parallel output mode. for xc17v08 and xc17v16 devices programmed to serial output mode, only the d0 pin is enabled for data output to the virtex series fpga serial configuration data input pin. in serial mode, the d[1-7] output pins remain in high impedance state and may be unconnected. for xc17v08 and xc17v16 devices programmed to parallel output mode, all d[0-7] output pins are enabled for byte-wide data output to the fpga selectmap configuration data input pins. the data/d0 pin is a bidirectional i/o during device programming. clk each rising edge on the clk input increments the internal address counter, when ce is active, oe is active, the internal address counter has not incremented past its terminal count (tc) value, and busy is low. note: the busy condition applies to only the xc17v08 and xc17v16. reset/oe the polarity of this input pin is programmable as either reset/ oe or oe/ reset . the polarity is set at the time of device programming. the device default is active-high reset, but compatibility with xilinx fpgas requires the polarity to be programmed with an active-low reset. when reset is active, the address counter is held at ?0?, and puts the data output in a high-impedance state. ce when high, this pin holds the internal address counter in reset, puts the data output in a high-impedance state, and forces the device into low-i cc standby mode. ceo chip enable output is connected to the ce input of the next prom in the daisy chain. this output is low when the ce and oe inputs are both active and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe goes inactive or ce goes high. busy (xc17v16 and xc17v08 only) asserting the busy input high prevents rising edges on clk from incrementing the internal address counter and maintains current data on the data pins. note: if the busy pin is floating, then the programmable option to internally tie busy to an internal pull-down resistor must be set during device programming. v pp programming voltage. no overshoot above the specified maximum voltage is permitted on this pin. for normal read operation, this pin must be connected to v cc . failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. caution! do not leave v pp floating! v cc and gnd positive supply and ground pins. prom pinouts for xc17v16 and xc17v08 pins not listed in ta bl e 1 are ?no connect.? ta b l e 1 : pinouts for xc17v16 and xc17v08 pin name 44-pin vqfp (vq44) 44-pin plcc (pc44) busy 24 30 d0 40 2 d1 29 35 d2 42 4 d3 27 33 d4 9 15 d5 25 31 d6 14 20 d7 19 25 clk 43 5 reset/oe (oe/reset ) 13 19 ce 15 21 gnd 6, 18, 28, 37, 41 3, 12, 24, 34, 43 ceo 21 27 v pp 35 41 v cc 8, 16, 17, 26, 36, 38 14, 22, 23, 32, 42, 44
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 4 r capacity pinout diagrams for xc17v16 and xc17v08 prom pinouts for xc17v04, xc17v02, and xc17v01 pins not listed in ta bl e 3 are ?no connect.? capacity ta bl e 2 : device capacities devices configuration bits xc17v16 16,777,216 xc17v08 8,388,608 1 2 3 4 5 6 7 8 9 10 11 vq44 top view nc nc nc nc d1 gnd d3 vcc d5 busy nc nc oe/reset d6 ce vcc vcc gnd d7 nc ceo nc nc nc nc nc nc gnd nc vcc d4 nc nc nc clk d2 gnd data(d0) nc vcc gnd vcc vpp nc ds073_12_101502 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 pc44 top view nc nc nc nc d1 gnd d3 vcc d5 busy nc nc oe/reset d6 ce vcc vcc gnd d7 nc ceo nc nc nc nc nc nc gnd nc vcc d4 nc nc nc clk d2 gnd data(d0) nc vcc gnd vcc vpp nc ds073_13_101502 ta b l e 3 : pinouts for xc17v04, xc17v02, and xc17v01 pin name 8-pin voic (v08) (1) 20-pin soic (so20) (1) 20-pin plcc (pc20) (1,2) 44-pin vqfp (vq44) (2) 44-pin plcc (pc44) (2) data 1 1 1 40 2 clk 2 3 3 43 5 reset/oe (oe/reset ) 38 81319 ce 4 10 10 15 21 gnd 5 11 11 18, 41 24, 3 ceo 6 13 13 21 27 v pp 718 183541 v cc 820 203844 notes: 1. xc17v01 available in these packages. 2. xc17v02 and xc17v04 available in these packages. ta b l e 4 : device capacities devices configuration bits xc17v04 4,194,304 xc17v02 2,097,152 xc17v01 1,679,360
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 5 r pinout diagrams for xc17v04, xc17v02, and xc17v01 notes: 1. xc1701 is available in these packages. 2. xc1702 and xc1704 are available in these packages. 1 2 3 4 5 6 7 8 9 10 11 vq44 top view (see note 2) nc nc nc nc nc nc nc nc nc nc nc nc oe/reset nc ce nc nc gnd nc nc ceo nc nc nc nc nc nc nc nc nc nc nc nc nc clk nc gnd data(d0) nc vcc nc nc vpp nc ds073_07_100702 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 pc44 top view (see note 2) nc nc nc nc nc nc nc nc nc nc nc nc oe/reset nc ce nc nc gnd nc nc ceo nc nc nc nc nc nc nc nc nc nc nc nc nc clk nc gnd data(d0) nc vcc nc nc vpp nc ds073_08_100702 vo8 top view (see note 1) ds073_09_110102 1 2 3 4 8 7 6 5 vcc vpp ceo gnd data(d0) clk oe/reset ce ds073_10_110102 so20 top view (see note 1) vcc nc vpp nc nc nc nc ceo nc gnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 data(d0) nc clk nc nc nc nc oe/reset nc ce pc20 top view (see notes 1, 2) ds073_11_101002 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 clk nc data(d0) vcc nc vpp nc nc nc nc nc ce gnd nc ceo nc nc nc nc oe/reset
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 6 r xilinx fpgas and compatible proms controlling proms connecting the fpga device with the prom. ? the data output(s) of the prom(s) drives the configuration data input(s) of the lead fpga device. ? the master fpga cclk output drives the clk input(s) of the prom(s). ? the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). ? the reset /oe input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. ? the prom ce input is best connected to the fpga done pin(s) and a pullup resistor. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 15 ma maximum. ? selectmap mode is similar to slave serial mode. the data is clocked out of the prom one byte per cclk instead of one bit per cclk cycle. see fpga data sheets for special configuration requirements. ta bl e 5 : xilinx fpgas and compatible proms device configuration bits prom xc2v40 360,096 xc17v01 xc2v80 635,296 xc17v01 xc2v250 1,697,184 xc17v02 xc2v500 2,761,888 xc17v04 xc2v1000 4,082,592 xc17v04 xc2v1500 5,659,296 xc17v08 xc2v2000 7,492,000 xc17v08 xc2v3000 10,494,368 xc17v16 xc2v4000 15,659,936 xc17v16 xc2v6000 21,849, 504 xc17v16 + xc17v08 xc2v8000 29,063,072 2 of xc17v16 xcv50 559,200 xc17v01 xcv100 781,216 xc17v01 xcv150 1,040,096 xc17v01 xcv200 1,335,840 xc17v01 xcv300 1,751,808 xc17v02 xcv400 2,546,048 xc17v04 xcv600 3,607,968 xc17v04 xcv800 4,715,616 xc17v08 xcv1000 6,127,744 xc17v08 xcv50e 630,048 xc17v01 xcv100e 863,840 xc17v01 xcv200e 1,442,016 xc17v01 xcv300e 1,875,648 xc17v02 xcv400e 2,693,440 xc17v04 xcv405e 3,430,400 xc17v04 xcv600e 3,961,632 xc17v04 xcv812e 6,519,648 xc17v08 xcv1000e 6,587,520 xc17v08 xcv1600e 8,308,992 xc17v08 xcv2000e 10,159,648 xc17v16 xcv2600e 12,922,336 xc17v16 xcv3200e 16,283,712 xc17v16 xc3s50 439,264 xc17v01 xc3s200 1,047,616 xc17v01 xc3s400 1,699,136 xc17v02 xc3s1000 3,223,488 xc17v04 xc3s1500 5,214,784 xc17v08 xc3s2000 7,673,024 xc17v08 xc3s4000 11,316,864 xc17v16 xc3s5000 13,271,936 xc17v16
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 7 r fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are established by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the configuration program from an external memory. the xilinx proms have been designed for compatibility with the master serial mode. upon power-up or reconfiguration, an fpga enters the master serial mode whenever all three of the fpga mode-select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. synchronization is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration interface. only one serial data line, two control lines, and one clock line are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function din pin on the fpga is used only for configurat ion, it must still be held at a defined level during normal operation. the xilinx fpga families take care of this automatically with an on-chip default pull-up/down resistor or keeper circuit. cascading configuration proms for multiple fpgas configured as a daisy-chain, or for future fpgas requiring larger configuration memories, cascaded proms provide additional memory. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and disables its data line. the second prom recognizes the low level on its ce input and enables its data output. see figure 3 . after configuration is complete, the address counters of all cascaded proms are reset if the fpga program pin goes low, assuming the prom reset polarity option has been inverted. standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high impedance state regardless of the state of the oe input. programming the devices can be programmed on programmers supplied by xilinx or qualified third-pa rty vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. selecting reset polarity and configuration modes the oe/ reset input polarity is programmable on all xc17v00 proms. in addition, the xc17v08 and xc17v16 can accommodate either serial or parallel configuration mode. the reset polarity and configuration mode are selectable through the programmer software. for compatibility with xilinx fpgas, the oe/ reset polarity must be programmed with reset active-low. ta bl e 6 : truth table for xc17v00 control inputs control inputs internal address outputs reset (1) ce data ceo i cc inactive low if address < tc (2) : increment if address > tc (2) : don?t change active high-z high low active reduced active low held reset high-z high active inactive high not changing high-z high standby active high held reset high-z high standby notes: 1. the xc17v00 reset input has programmable polarity 2. tc = terminal count, highest address value.
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 8 r figure 3: (a) master serial mode (b) virtex selectmap mode (dotted lines indicates optional connection) program din cclk init done first prom data ceo busy busy clk ce optional slave fpgas with identical configurations fpga (low resets the address pointer) v cc vpp optional daisy-chained fpgas with different configurations oe/reset dout modes (1) busy busy virtex selectmap mode, xc17v16 and xc17v0 8 only. 4.7k 4.7k v cc v cc v cc vpp v cc v cc v cc (2) master serial mode ds073_03_033106 (1) for mode pin connections, refer to the appropriate fpga data sheet or user guide. (2) for specific done resistor recommendations, refer to the appropriate fpga data sheet or user guide. cascaded prom data clk ce oe/reset program virtex selectmap busy cs write init d[0:7] cclk done clk d[0:7] ce oe/reset first prom second prom modes (3) 3.3v external osc (4) ceo 4.7k (2) v cc v cc vpp v cc 1k i/o (1) 8 i/o (1) 1k (1) cs and write must be pulled down to be used as i/o. one option is shown. (2) for specific done resistor recommendations, refer to the appropriate fpga data sheet or user guide. (3) for mode pin connections, refer to the appropriate fpga data sheet or user guide. (4) external oscillator required for fpga slave selectmap modes. clk d[0:7] ce oe/reset ceo v cc v cc vpp
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 9 r absolute maximum ratings (1) operating conditio ns (3v supply) dc characteristics over operating condition symbol description conditions units v cc supply voltage relative to gnd ?0.5 to +7.0 v v pp supply voltage relative to gnd ?0.5 to +12.5 v v in input voltage relative to gnd ?0.5 to v cc +0.5 v v ts voltage applied to high-z output ?0.5 to v cc +0.5 v t stg storage temperature (ambient) ?65 to +150 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc (1) supply voltage relative to gnd (t a = 0 c to +70 c) commercial 3.0 3.6 v supply voltage relative to gnd (t a = ?40 c to +85 c) industrial 3.0 3.6 v t vcc (2) v cc rise time from 0v to nominal voltage 1.0 50 ms notes: 1. during normal read operation v pp must be connected to v cc . 2. at power up, the device requires the v cc power supply to monotonically rise from 0v to nominal voltage within the specified v cc rise time. if the power supply cannot meet this requirement, then the device may not power-on-reset properly. symbol description min max units v ih high-level input voltage 2 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ?3 ma) 2.4 ? v v ol low-level output voltage (i ol = +3 ma) ? 0.4 v i cca supply current, active mode (at maximum frequency) (xc17v16 and xc17v08 only) ? 100 m a i cca supply current, active mode (at maximum frequency) (xc17v04, xc17v02, and xc17v01 only) ?15 m a i ccs supply current, standby mode ? 1 ma i l input or output leakage current ?10 10 a c in input capacitance (v in = gnd, f = 1.0 mhz) ? 15 pf c out output capacitance (v in = gnd, f = 1.0 mhz) ? 15 pf
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 10 r ac characteristics over operating cond ition for xc17v04, xc17v02, and xc17v01 symbol description min max units t oe oe to data delay ? 30 ns t ce ce to data delay ? 45 ns t cac clk to data delay ? 45 ns t df ce or oe to data float delay (2,3) ?50ns t oh data hold from ce , oe , or clk (3) 0?ns t cyc clock periods 67 ? ns t lc clk low time (3) 25 ? ns t hc clk high time (3) 25 ? ns t sce ce setup time to clk (to guarantee proper counting) 25 ? ns t hce ce hold time to clk (to guarantee proper counting) 0 ? ns t hoe oe hold time (guarantees counters are reset) 25 ? ns t ceh ce high time (guarantees counters are reset) 20 ? ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t ceh high, 2 s, t ce = 2 s. 6. if t hoe high, 2 s, t oe = 2 s. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds073_04_14102005 t cyc tceh notes: 1 the xc17v00 reset/oe input polarity is programmable. the reset/oe input is shown in the timing diagram with active-high reset polarity. timing specifications are identical for both polarity settings. 2 the diagram shows timing relationships. the diagram is not reflective of actual fpga signal sequences. see the appropriate fpga data sheet or user guide for actual configuration signal sequences.
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 11 r ac characteristics over operatin g condition for xc17v16 and xc17v08 symbol description min max units t oe oe to data delay ? 15 ns t ce ce to data delay ? 20 ns t cac clk to data delay (2) ?20ns t df ce or oe to data float delay (3,4) ?35ns t oh data hold from ce , oe , or clk (4) 0?ns t cyc clock periods 50 ? ns t lc clk low time (4) 25 ? ns t hc clk high time (4) 25 ? ns t sce ce setup time to clk (to guarantee proper counting) 25 ? ns t hce ce hold time to clk (to guarantee proper counting) 0 ? ns t hoe oe hold time (guarantees counters are reset) 25 ? ns t sbusy busy setup time 5 ? ns t hbusy busy hold time 5 ? ns t ceh ce high time (guarantees counters are reset) 20 ? ns notes: 1. ac test load = 50 pf. 2. when busy = 0. 3. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 4. guaranteed by design, not tested. 5. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 6. if t ceh high, 2 s, t ce = 2 s. 7. if t hoe high, 2 s, t oe = 2 s. reset/oe (1) ce clk busy (2) data t ce t oe t lc t sce t sce t hce t hoe t cac t sbusy t hbusy t oh t df t oh t hc ds073_05_031606 t cyc tceh note: 1 the xc17v00 reset/oe input polarity is programmable. the reset/oe input is shown in the timing diagram with active-high rese t polarity. timing specifications are identical for both polarity settings. 2. if busy is inactive (low) during a rising clk edge, then new data appears at time t cac after the rising clk edge. if busy is active (high) during a rising clk edge, then there is no corresponding change to data.
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 12 r ac characteristics over oper ating condition when cascading symbol description min max units t cdf clk to data float delay (2,3) ?50ns t ock clk to ceo delay (3) ?30ns t oce ce to ceo delay (3) ?35ns t ooe reset/oe to ceo delay (3) ?30ns notes: 1. ac test load = 50 pf 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. clk data ce ceo first bit last bit t cdf ds026_07_102005 reset/oe t ock t ooe t oce notes: 1 the xc17v00 reset/oe input polarity is programmable. the reset/oe input is shown in the timing diagram with active-high reset polarity. timing specifications are identical for both polarity settings. 2 the diagram shows timing of the first bit and last bit for one prom with respect to signals involved in a cascaded situation . the diagram does not show timing of data as one prom transfers control to the next prom. the shown timing information must be applied appropriately to each prom in a cascaded situation to understand the timing of data during the transfer of control from one prom to the next.
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 13 r ordering information valid ordering combinations marking information due to the small size of the commercial serial prom packages, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows: xc17v16vq44c xc17v08vq44c xc17v04pc20c xc17v02pc20c xc17v01pc20c xc17v16pc44c xc17v08pc44c xc17v 04pc44c xc17v02pc44c xc17v01vo8c xc17v16vq44i xc17v08vq44i xc17v04vq44c xc17v02vq44c xc17v01so20c xc17v16pc44i xc17v08pc44i xc17v 04pc20i xc17v02pc20i xc17v01pc20i xc17v04pc44i xc17v02pc44i xc17v01vo8i xc17v04vq44i xc17v02vq44i xc17v01so20i xc17v16 pc44 c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = ?40 to +85 c) package type vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier v08 = 8-pin plastic small outline thin package pc20 = 20-pin plastic leaded chip carrier so20 = 20-pin plastic small outline package device number xc17v16 xc17v08 xc17v04 xc17v02 xc17v01 xc17v16 pc44 c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = ?40 to +85 c) package type vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier v08 = 8-pin plastic small outline thin package pc20 = 20-pin plastic leaded chip carrier so20 = 20-pin plastic small outline package device number xc17v16 xc17v08 xc17v04 xc17v02 xc17v01
xc17v00 series configuration proms ds073 (v1.11) june 7, 2007 www.xilinx.com product specification 14 r revision history the following table shows the revision history for this document. . date version revision 07/26/00 1.0 initial xilinx release. 10/09/00 1.1 updated 20-pin plcc pinouts. 11/16/00 1.2 updated pinouts fo r xc17v16 and xc17v08, i cca dc characteristic from standby to active mode; c in and c out from 10 pf to 15 pf, added i ccs for xc17v16 and xc17v08 at 500 a. 02/20/01 1.3 added note to pinouts for ?no connect,? updated figure 3. 04/04/01 1.4 added xc2v products to compatible prom table, updated figure 3 , updated text for virtex-ii fpgas. 10/09/01 1.5 corrected bitstream length for scv405e, added power-on supply requirements and note for power-on reset, updated configuration bits for virtex-ii devices, removed cf from figure 3 , and updated fpga list. 02/27/02 1.6 added virtex-ii pro? fpgas to the xilinx fpgas and compatible proms, page 6 . 06/14/02 1.7 made additions and changes to xilinx fpgas and compatible proms, page 6 . 07/29/02 1.8 added virtex-ii pro fpgas to xilinx fpgas and compatible proms, page 6 . 11/05/02 1.9 added pinout diagrams, changed xilinx fpgas and compatible proms, page 6 , and added footnotes to ac characteristics over operating conditi on for xc17v04, xc17v02, and xc17v01, page 10 and ac characteristics over operating condition for xc17v16 and xc17v08, page 11 . 04/10/03 1.10 added spartan-3 fpgas to truth table for xc17v00 control inputs, page 7 . 06/07/07 1.11 ? figure 2, page 2 updated to show correct three-st ate control on output data buses. ? corrected xc3s50 bitstream size in xilinx fpgas and compatible proms, page 6 . ? added section selecting reset polarity and configuration modes, page 7 . ? removed maximum soldering temperature (t sol ) from "absolute maximum ratings (1) ," page 9 . refer to xilinx device package user guide for package soldering guidelines. ? added notes to timing diagram under ac characteristics over operating condition for xc17v04, xc17v02, and xc17v01, page 10 for clarification. ? added notes and updated timing diagram ac characteristics over operating condition for xc17v16 and xc17v08, page 11 for clarification. ? reversed polarity of reset/oe signal in timing diagram under , page 12 for consistency and added notes for clarification.

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